LPRTC_PSCLR_EN=Val_0x0, LPRTC_WEN=Val_0x0, LPRTC_MASK=Val_0x0, LPRTC_EN=Val_0x0, LPRTC_IEN=Val_0x0
Counter Control Register
| LPRTC_IEN | Controls the interrupt enable. 0 (Val_0x0): Disables the interrupt generation. 1 (Val_0x1): Enables the interrupt generation. |
| LPRTC_MASK | Controls the interrupt mask. Determines whether an internally generated interrupt shall assert the IRQ line. 0 (Val_0x0): Unmasks the interrupt. 1 (Val_0x1): Masks the interrupt. |
| LPRTC_EN | Controls counting in the counter. 0 (Val_0x0): Disables the counter. 1 (Val_0x1): Enables the counter. |
| LPRTC_WEN | Controls the wrap enable. Forces the counter to wrap to 0 when a match occurs, instead of waiting until the maximum count is reached. 0 (Val_0x0): Disables the wrap. 1 (Val_0x1): Enables the wrap. |
| LPRTC_PSCLR_EN | Controls the usage of the prescaler feature. 0 (Val_0x0): Disables the prescaler. 1 (Val_0x1): Enables the prescaler. |